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asahi kasei [AK4348] ms0532-e-00 2006/07 - 1 - general description the AK4348 is an 8-channel 24bit dac operating off of a single +3.3v power supply. the outputs are single-ended, and it samples at rates from 8khz to 192khz. it uses akm?s advanced multi-bit architecture for the modulator to achieve a wide dynamic range while preserving linearity for improved thd+n performance. the output circuit includes a switched-cap filter and a second-order analog low pass filter, minimizing the need for external filtering. features ? sampling rate: 8khz to 192khz ? 24-bit 8 times digital filter with slow roll-off option ? dr, s/n: 104db ? thd+n: -90db ? high tolerance to clock jitter ? single ended output buffer with second order analog lpf ? digital de-emphasis for 32, 44.1 & 48khz sampling ? zero detect function ? channel independent digital attenuator (linear 256 steps) ? 3-wire serial or i 2 c control ? i/f format: msb justified, lsb justified (16-, 20-, 24-bit), i 2 s, tdm ? master clock: 256fs, 384fs, 512fs or 768fs or 1152fs (normal speed mode) 128fs, 192fs, 256fs or 384fs (double speed mode) 128fs or 192fs (quad speed mode) ? power supply: 2.7v to 3.6v ? ta = ? 20 85 c (ef), ? 40 85 c (vf) ? package: 30-pin vsop ? ak4359 pin compatible scf dac datt dzf lout1 scf dac datt rout1 scf dac datt lout2 scf dac datt rout2 scf dac datt lout3 scf dac datt rout3 audio i/f control register AK4348 mclk lrck bick 3-wire or i2c sdti1 sdti2 sdti3 pcm scf dac datt lout4 scf dac datt rout4 sdti4 lpf lpf lpf lpf lpf lpf lpf lpf 3.3v 192khz 24-bit 8-channel dac AK4348
asahi kasei [AK4348] ms0532-e-00 2006/07 - 2 - ? ordering guide AK4348ef -20 +85 c 30pin vsop AK4348vf -40 +85 c 30pin vsop akd4348 evaluation board for AK4348 ? pin layout 6 5 4 3 2 1 mclk bick lrck sdti1 rstb smute/csn/cad0 7 dif0/cdti/sda 8 dzf1 tdm0/dzf2 avdd avss vcom lout1 rout1 p/s AK4348 top view 10 9 sdti2 sdti3 sdti4 11 dif1 12 lout2 rout2 lout3 rout3 25 26 27 28 29 30 24 23 21 22 20 19 acks/cclk/scl dem0/cad1 13 dvdd 14 lout4 rout4 18 17 dvss 15 dem1/i2c 16 ? compatibility with ak4359 function ak4359 AK4348 power supply voltage 4.5 to 5.5v 2.7 to 3.6v #29 pin function in parallel control mode ?l? output tdm0 pin (pull-down pin) chip address for 3-wire up i/f n/a cad1 (cad0 is fixed.) chip address for i2c up i/f cad0 cad0, cad1
asahi kasei [AK4348] ms0532-e-00 2006/07 - 3 - pin/function no. pin name i/o function 1 mclk i master clock input an external ttl clock should be input on this pin. 2 bick i audio serial data clock 3 sdti1 i dac1 audio serial data input 4 lrck i l/r clock 5 rstb i reset mode when at ?l?, the AK4348 is in reset mode. the AK4348 must be reset once upon power-up. smute i soft mute in parallel control mode ?h?: enable, ?l?: disable csn i chip select in serial 3-wire mode 6 cad0 i chip address in serial i2c mode acks i auto setting mode in parallel control mode ?l?: manual setting mode, ?h?: auto setting mode cclk i control data clock in serial 3-wire control mode 7 scl control data clock in serial i2c control mode dif0 i audio data interface format in parallel control mode cdti i control data input in serial 3-wire control mode 8 sda i/o control data in serial i2c control mode 9 sdti2 i dac2 audio serial data input 10 sdti3 i dac3 audio serial data input 11 sdti4 i dac4 audio serial data input 12 dif1 i audio data interface format cad1 i chip address in serial control mode 13 dem0 i de-emphasis filter enable 14 dvdd digital power supply, +2.7 +3.6v 15 dvss digital ground i2c i p i/f mode select in serial control mode ?l?: 3-wire serial, ?h?: i 2 c bus 16 dem1 i de-emphasis filter enable in parallel control mode 17 rout4 o dac4 right channel analog output 18 lout4 o dac4 left channel analog output 19 rout3 o dac3 right channel analog output 20 lout3 o dac3 left channel analog output 21 rout2 o dac2 right channel analog output 22 lout2 o dac2 left channel analog output 23 p/s i parallel/serial control mode select (internal pull-up pin) ?l?: serial control mode, ?h?: parallel control mode 24 rout1 o dac1 right channel analog output 25 lout1 o dac1 left channel analog output 26 vcom o common voltage, avdd/2 normally connected to avss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 27 avss - analog ground 28 avdd - analog power supply, +2.7 +3.6v tdm0 i tdm i/f format mode in parallel control mode (internal pull-down pin) ?l?: normal mode, ?h?: tdm 256 mode 29 dzf2 o data zero input detect in serial control mode 30 dzf1 o data zero input detect note: all input pins except p/s and tdm0 pins should not be left floating.
asahi kasei [AK4348] ms0532-e-00 2006/07 - 4 - ? handling of unused pins unused i/o pins should be resolved as shown in this table. classificatio n pin name setting analog lout4-1, rout4-1 leave open. dzf2-1 leave open. sdti4-1 smute (parallel control mode) connect to dvss. digital dem0, dif1 (serial control mode) connect to dvdd or dvss. absolute maximum ratings (avss, dvss=0v; note 1) parameter symbol min max units power supplies analog digital |avss-dvss| (note 2) avdd dvdd ? gnd -0.3 -0.3 - 4.6 4.6 0.3 v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina -0.3 avdd+0.3 v digital input voltage vind -0.3 dvdd+0.3 v AK4348ef ta -20 85 c ambient operating temperature AK4348vf ta -40 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. note 2. avss and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 1) parameter symbol min typ max units power supplies (note 1) analog digital avdd dvdd 2.7 2.7 3.3 3.3 3.6 3.6 v v note 3. the power up sequence between avdd and dvdd is not critical. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK4348] ms0532-e-00 2006/07 - 5 - analog characteristics (ta=25 c; avdd, dvdd=3.3v; fs=44.1khz; bick=64fs; signal frequency=1khz; 24bit input data; measurement frequency=20hz 20khz; r l 5k ? ; unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics (note 4) fs=44.1khz bw=20khz 0dbfs -60dbfs -90 -40 -80 - db db fs=96khz bw=40khz 0dbfs -60dbfs -86 -37 - - db db thd+n fs=192khz bw=40khz 0dbfs -60dbfs -86 -37 - - db db dynamic range (-60dbfs with a-weighted) (note 5) 96 104 db s/n (a-weighted) (note 6) 96 104 db interchannel isolation (1khz) 80 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy gain drift 100 - ppm/ c output voltage (note 7) 2.09 2.24 2.39 vpp load resistance (note 8) 5 k ? load capacitance 25 pf power supplies power supply current (avdd+dvdd) normal operation (rstb pin = ?h?, fs 96khz) normal operation (rstb pin = ?h?, fs=192khz) reset mode (rstb pin = ?l?) (note 9) 45 52 33 72 78 133 ma ma a note 4. measured by audio precision system two. refer to the evaluation board manual. note 5. 100db when using 16bit data. note 6. s/n does not depend on input data resolution. note 7. full scale voltage (0db). output voltage scales with the voltage of avdd pin. aout (typ. @0db) = 2.24vpp avdd/3.3 note 8. for ac-load. note 9. p/s pin is tied to dvdd and the other all digital input pins including clock pins (mclk, bick, lrck) are tied to dvss.
asahi kasei [AK4348] ms0532-e-00 2006/07 - 6 - sharp roll-off filter characteristics (ta = 25 c; avdd, dvdd = 2.7 3.6v; fs = 44.1khz; dem = off; slow = ?0?) parameter symbol min typ max units digital filter passband 0.05db (note 10) -6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 10) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay (note 11) gd - 19.3 - 1/fs digital filter + scf frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - + 0.06/-0.10 + 0.06/-0.13 + 0.06/-0.51 - - - db db db note 10. the passband and stopband frequencies scale with fs(system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. note 11. calculated delay time caused by the digital filter. this time is measured from when the serial data of both channels is in the input register to the output of the analog signal. slow roll-off filter characteristics (ta = 25 c; avdd, dvdd = 2.7~3.6v; fs = 44.1khz; dem = off; slow = ?1?) parameter symbol min typ max units digital filter passband 0.04db (note 12) -3.0db pb 0 - 18.2 8.1 - khz khz stopband (note 12) sb 39.2 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay (note 11) gd - 19.3 - 1/fs digital filter + scf frequency response 20.0khz 40.0khz 80.0khz fs=44.khz fs=96khz fs=192khz fr fr fr - - - +0.1/-4.3 +0.1/-3.3 +0.1/-3.7 - - - db db db note 12. the passband and stopband frequencies scale with fs. for example, pb = 0.185fs (@ 0.04db), sb = 0.888fs. dc characteristics (ta = 25 c; avdd, dvdd = 2.7 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - 30%dvdd v v high-level output voltage (iout = -80a) low-level output voltage (iout = 80a) voh vol dvdd-0.4 - - - 0.4 v v input leakage current (note 13) iin - - 10 a note 13. p/s pin has an internal pull-up device and tdm0 pin has an internal pull-down device, nominally 100k ? .
asahi kasei [AK4348] ms0532-e-00 2006/07 - 7 - switching characteristics (ta = 25 c; avdd, dvdd = 2.7 3.6v; c l = 20pf) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 2.048 40 11.2896 36.864 60 mhz % lrck frequency normal mode (tdm0= ?0?, tdm1= ?0?) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 60 120 45 48 96 192 55 khz khz khz % tdm256 mode (tdm0= ?1?, tdm1= ?0?) normal speed mode high time low time fsn tlrh tlrl 8 1/256fs 1/256fs 48 khz ns ns tdm128 mode (tdm0= ?1?, tdm1= ?1?) normal speed mode double speed mode high time low time fsn fsd tlrh tlrl 8 60 1/128fs 1/128fs 48 96 khz khz ns ns audio interface timing bick period bick pulse width low pulse width high bick ? ? to lrck edge (note 14) lrck edge to bick ? ? (note 14) sdti hold time sdti setup time tbck tbckl tbckh tblr tlrb tsdh tsds 81 30 30 20 20 10 10 ns ns ns ns ns ns ns control interface timing (3-wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn high time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 15) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 - 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf reset timing rstb pulse width (note 16) trst 150 ns
asahi kasei [AK4348] ms0532-e-00 2006/07 - 8 - note 14. bick rising edge must not occur at the same time as lrck edge. note 15. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 16. the AK4348 can be reset by bringing rstb pin = ?l?. note 17. i 2 c is a registered trademark of philips semiconductors. ? timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr audio serial interface timing
asahi kasei [AK4348] ms0532-e-00 2006/07 - 9 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta sto p start start sto p tsu:sto vil vih vil tsp i 2 c bus mode timing trst vil rstb reset timing
asahi kasei [AK4348] ms0532-e-00 2006/07 - 10 - operation overview ? system clock the external clocks required to operate the AK4348 are mclk, lrck and bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two methods to set mclk frequency. in manual setting mode (acks bit = ?0?: register 00h), the sampling speed is set by dfs0-1 bits (table 1). the frequency of mclk at each sampling speed is set automatically. (table 2~table 4) in auto setting mode (acks bit = ?1?: default), the mclk frequency is detected automatically (table 5), and the internal master clock is set to the appropriate frequency (table 6) and it is not necessary to set dfs0-1. in parallel control mode, the sampling speed can be set by only the acks pin. when acks pin = ?l?, the AK4348 operates by normal speed mode. when acks pin = ?h?, auto setting mode is enabled. the parallel control mode does not support 128fs and 192fs of double speed mode. all external clocks (mclk, bick and lrck) should be present whenever the AK4348 is in normal operation mode (rstb pin = ?h?). if these clocks are not provided, the AK4348 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. the AK4348 should be reset by setting rstb pin = ?l? after threse clocks are provided. if the external clocks are not present, the AK4348 should be in the power-down mode (rstb pin = ?l?). after exiting reset(rstb = ? ?) at power-up, the AK4348 is in the power-down mode until mclk is input. dfs1 dfs0 sampling rate (fs) 0 0 normal speed mode 8khz~48khz default 0 1 double speed mode 60khz~96khz 1 0 quad speed mode 120khz~192khz table 1. sampling speed (manual setting mode) lrck mclk bick fs 256fs 384fs 512fs 768fs 1152fs 64fs 32.0khz 8.1920mhz 12.2880mhz 16.3840mhz 24.5760mhz 36.8640mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz n/a 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz n/a 3.0720mhz table 2. system clock example (normal speed mode @manual setting mode) lrck mclk bick fs 128fs 192fs 256fs 384fs 64fs 88.2khz 106896mhz 16.9344mhz 22.5792mhz 33.8688mhz 5.6448mhz 96.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 6.1440mhz table 3. system clock example (double speed mode @manual setting mode) lrck mclk bick fs 128fs 192fs 64fs 176.4khz 22.5792mhz 33.8688mhz 106896mhz 192.0khz 24.5760mhz 36.8640mhz 12.2880mhz table 4. system clock example (quad speed mode @manual setting mode)
asahi kasei [AK4348] ms0532-e-00 2006/07 - 11 - mclk sampling speed 1152fs normal (fs 32khz) 512fs 768fs normal 256fs 384fs double 128fs 192fs quad table 5. sampling speed (auto setting mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48.0khz - - - - 24.5760 36.8640 - normal 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - double 176.4khz 22.5792 33.8688 - - - - - 192.0khz 24.5760 36.8640 - - - - - quad table 6. system clock example (auto setting mode)
asahi kasei [AK4348] ms0532-e-00 2006/07 - 12 - ? audio serial interface format in parallel control mode, the dif0-1 and tdm0 pins can select eight serial data modes (table 7). the register value of dif0-1 and tdm0bits are ignored. in serial control mode, the dif0-2 and tdm0-1 bits shown in table 8 can select 11 serial data modes. the default format is mode 2 (24-bit msb justified format in normal mode). the setting of dif1 pin is ignored. in all modes the audio data is msb-first, 2?s complement format and is latched on the rising edge of bick. mode 2 can be used for 16/20-bit msb justified formats by zeroing the unused lsb?s. in parallel control mode, when the tdm0 pin = ?h?, the audio interface format is tdm256 mode (table 7). the audio data of all dacs (eight channels) is input to the sdti1 pin. the input data to sdti2-4 pins is ignored. bick should be fixed to 256fs. ?h? time and ?l? time of lrck should be at least 1/256fs. the audio data is msb-first, 2?s complement format. the input data to sdti1 pin is latched on the rising edge of bick. in serial control mode, when the tdm0 bit = ?1? and the tdm1 bit = ?0?, the audio interface format is tdm 256 mode (table 8), and the audio data of all dacs (eight channels) is input to the sdti1 pin. the input data to sdti2-4 pins is ignored. bick should be fixed to 256fs. ?h? time and ?l? time of lrck should be at least 1/256fs. the audio data is msb-first, 2?s complement format. the input data to sdti1 pin is latched on the rising edge of bick. in tdm128 mode (tdm0 bit = ?1? and tdm1 bit = ?1?, table 8), the audio data of dacs (four channels; l1, r1, l2, r2) is input to the sdti1 pin. the other four data (l3, r3, l4, r4) is input to the sdti2 pin. the input data to sdti3-4 pins is ignored. bick should be fixed to 128fs. the audio data is msb-first, 2?s complement format. the input data to sdti1-2 pins is latched on the rising edge of bick. mode tdm0 dif1 dif0 sdti format lrck bick figure 0 l l l 16-bit lsb justified h/l 32fs figure 1 1 l l h 20-bit lsb justified h/l 40fs figure 2 2 l h l 24-bit msb justified h/l 48fs figure 3 normal 3 l h h 24-bit i 2 s compatible l/h 48fs figure 4 h l l n/a h l h n/a 5 h h l 24-bit msb justified 256fs figure 5 tdm256 6 h h h 24-bit i 2 s compatible 256fs figure 6 table 7. audio data formats (parallel control mode) mode tdm1 tdm0 dif2 dif1 dif0 sdti format lrck bick figure 0 0 0 0 0 0 16-bit lsb justified h/l 32fs figure 1 1 0 0 0 0 1 20-bit lsb justified h/l 40fs figure 2 2 0 0 0 1 0 24-bit msb justified h/l 48fs figure 3 3 0 0 0 1 1 24-bit i 2 s compatible l/h 48fs figure 4 normal 4 0 0 1 0 0 24-bit lsb justified h/l 48fs figure 2 0 1 0 0 0 n/a 0 1 0 0 1 n/a 5 0 1 0 1 0 24-bit msb justified 256fs figure 5 6 0 1 0 1 1 24-bit i 2 s compatible 256fs figure 6 tdm256 7 0 1 1 0 0 24-bit lsb justified 256fs figure 7 1 1 0 0 0 n/a 1 1 0 0 1 n/a 8 1 1 0 1 0 24-bit msb justified 128fs figure 8 9 1 1 0 1 1 24-bit i 2 s compatible 128fs figure 9 tdm128 10 1 1 1 0 0 24-bit lsb justified 128fs figure 10 table 8. audio data formats (serial control mode, default: mode 2)
asahi kasei [AK4348] ms0532-e-00 2006/07 - 13 - sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 ( 32fs ) ( 64fs ) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 1514 6543210 lch data rch data figure 1. mode 0 timing sdti lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1,4 timing lrck bick ( 64fs ) sdti 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 224 23 30 22 1 0don?t care 23 22 23 figure 3. mode 2 timing
asahi kasei [AK4348] ms0532-e-00 2006/07 - 14 - lrck bick ( 64fs ) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 224 23 25 22 1 0 don?t care 23 23 figure 4. mode 3 timing lrck bick(256fs) sdti1(i) 256 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 22 23 23 23 23 23 23 23 23 23 figure 5. mode 5 timing lrck bick(256fs) sdti1(i) 256 bick 23 0 l1 32 bick 23 0 r1 32 bick 23 0 l2 32 bick 23 0 r2 32 bick 23 0 l3 32 bick 23 0 r3 32 bick 23 0 l4 32 bick 23 0 r4 32 bick 23 figure 6. mode 6 timing lrck bick(256fs) sdti1(i) 256 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 23 23 23 23 23 23 23 23 23 figure 7. mode 7 timing
asahi kasei [AK4348] ms0532-e-00 2006/07 - 15 - lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 figure 8. mode 8 timing lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 figure 9. mode 9 timing lrck bick(128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 figure 10. mode 10 timing
asahi kasei [AK4348] ms0532-e-00 2006/07 - 16 - ? de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15 s). the digital de-emphasis filter is always off when the AK4348 is operated in double or quad speed modes. in serial control mode, the dem0-1 bits are valid for the dac enabled by the dema-d bits. in parallel control mode, the dem0-1 pins are valid. dem1 dem0 mode 0 0 44.1khz 0 1 off 1 0 48khz 1 1 32khz table 9. de-emphasis filter control (normal speed mode) ? output volume the AK4348 includes channel independent digital volume controls (att) with 256 linear steps, including mute. the volume controls are in front of the dac and can attenuate the input data from 0db to ?48db, and mute. when changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. the transition time of 1 level and all 256 levels is shown in table 10 . the attenuation level is calculated by att = 20 log 10 (att_data / 255) [db] and mute at att_data = ?0?. transition time sampling speed 1 level 255 to 0 normal speed mode 4lrck 1020lrck double speed mode 8lrck 2040lrck quad speed mode 16lrck 4080lrck table 10. att transition time ? zero detection when the input data at all channels are continuously zeros for 8192 lrck cycles, the AK4348 has a zero detect function detailed in table 11. the dzf pin immediately goes to ?l? if the input data for each channel is not zero after the dzf pin is ?h?. if the rstn bit is ?0?, the dzf pin goes to ?h?. the dzf pin goes to ?l? after 4 to 5lrck cycles if the input data of each channel is not zero after the rstn bit returns to ?1?. the zero detect function can be disabled by the dzfe bit. in this case, both dzf pins are always ?l?. when one of the pw1-4 bits is set to ?0?, the input data of the dac for which the pw bit is set to ?0? should be zero in order to enable zero detection of the other channels. when all pw1-4 bits are set to ?0?, both dzf pins are fixed to ?l?. the dzfb bit can invert the polarity of the dzf pin. in parallel control mode, the zero detect function is disabled and the dzf1 pin is fixed to ?l?. dzf pin operations dzf1 and?ed output of zero detection flag of each channel set to ?1? in 0ch register dzf2 and?ed output of zero detection flag of each channel set to ?1? in 0dh register table 11. dzf pins operation
asahi kasei [AK4348] ms0532-e-00 2006/07 - 17 - ? soft mute operation soft mute operation is performed in the digital domain. when the smute bit goes to ?1?, the output signal is attenuated by - during the att_data att transition time (table 10) from the current att level. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during the att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective when changing the signal source without stopping the signal transmission. smute attenuation dzf pin att level - aout 8192/fs gd gd (1) (2) (3) (4) (1) notes: (1) att_data att transition time (table 10). for example, in normal speed mode, this time is 1020lrck cycles (1020/fs) at att_data=255. (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at each channel is continuously zero for 8192 lrck cycles, the dzf pin of each channel goes to ?h?. the dzf pin immediately goes to ?l? if input data are not zero after going dzf ?h?. in parallel control mode, the dzf pin is fixed to ?l? regardless of the state of smute pin. figure 11. soft mute and zero detection (dzfb bit = ?0?)
asahi kasei [AK4348] ms0532-e-00 2006/07 - 18 - ? system reset the AK4348 should be reset once by bringing rstb pin = ?l? upon power-up. the AK4348 is powered up and the internal timing starts clocking by lrck ? ? after exiting reset and power down state by mclk. the AK4348 is in the power-down mode until mclk and lrck are input. ? power on/off timing all dacs are placed in the power-down mode by bringing rstb pin ?l? and the registers are initialized. the analog outputs go to vcom. since some click noise occurs at the edge of the rstb signal, the analog output should be muted externally if the click noise influences system application. each dac can be powered down by setting each power-down bit (pw1-4 bits) to ?0?. in this case, the registers are not initialized and the corresponding analog outputs go to vcom. since some click noise occurs at the edge of the rstb signal, the analog output should be muted externally if the click noise influences system application. rstb pin power reset normal operation clock in mclk,lrck,bick dac in (digital) dac out (analog) external mute mute on (5) dzf1/dzf2 don?t care ?0?data gd (1) (3) (4) (6) gd (3) mute on ?0?data don?t care internal state (2) (2) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs are vcom at power-down mode. (3) click noise occurs at the edge of rstb signal. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the power-down mode (rstb pin = ?l?). (5) mute the analog output externally if the click noise (3) influences the system application. the timing example is shown in this figure. (6) dzf pins are ?l? in the power-down mode (rstb pin = ?l?). (dzfb bit = ?0?) figure 12. power-down/up sequence example
asahi kasei [AK4348] ms0532-e-00 2006/07 - 19 - ? reset function (rstn bit) when the rstn bit = ?0?, the internal circuit of the dac is powered down but the registers are not initialized. the analog outputs go to vcom voltage and the dzf pins go to ?h? when the dzfb bit = ?0?. figure 13 shows the example of reset by the rstn bit. when the rstn bit = ?0?, click noise is decreased at no clock state. internal state rstn bit digital block power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) dzf (3) (1) (2) normal operation 2/fs(5) internal rstn bit 2~3/fs (6) 3~4/fs (6) don?t care (4) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs go to vcom voltage. (3) small click noise occurs at the edges(? ?) of the internal timing of rstn bit. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn bit = ?0?). (5) dzf pins go to ?h? when the rstn bit becomes ?0?, and go to ?l? at 2/fs after rstn bit becomes ?1?. (6) there is a delay, 3~4/fs from rstn bit ?0? to the internal rstn bit ?0?, and 2~3/fs from rstn bit ?1? to the internal rstn bit ?1?. figure 13. reset sequence example (dzfb bit = ?0?)
asahi kasei [AK4348] ms0532-e-00 2006/07 - 20 - ? register control interface the AK4348 controls its functions via registers. two types of control mode can be used to write to the internal registers. in i 2 c-bus mode, the chip address is determined by the state of the cad0-1 pins. in 3-wire mode, the chip address can be selected by the state of the cad1 pin. rstb pin = ?l? initializes the registers to their default values. writing ?0? to the rstn bit resets the internal timing circuit, but the registers are not initialized. * the AK4348 does not support the read command. * when the AK4348 is in the power down mode (rstb bit = ?l?) or the mclk is not provided, writing to control registers is prohibited. * when the state of p/s pin is changed, the AK4348 should be reset by rstb bit = ?l?. * in serial control mode, the setting of parallel pins is invalid. function parallel control mode serial control mode double sampling mode at 128/192fs - o de-emphasis o o smute o o zero detection - o 24bit lsb justified format - o tdm256 mode o o tdm128 mode - o table 12. function table (o: supported, -: not supported) (1) 3-wire serial control mode (i2c pin = ?l?) internal registers may be written to via the 3-wire p interface pins (csn, cclk and cdti). the data on this interface consists of chip address (2-bits, c1/0; c1=cad1 and c0 is fixed to ?1?), read/write (1-bit; fixed to ?1?, write only), register address (msb first, 5-bits) and control data (msb first, 8-bits). the AK4348 latches the data on the rising edge of cclk, so data should clocked in on the falling edge. the writing of data becomes valid by the rising edge of csn. the clock speed of cclk is 5mhz (max). cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a 1 a 2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (c1=cad1, c0=?1?) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 14. control i/f timing
asahi kasei [AK4348] ms0532-e-00 2006/07 - 21 - (2) i 2 c-bus control mode (i2c pin = ?h?) the AK4348 supports fast-mode i 2 c-bus system (max: 400khz). figure 15 shows the data transfer sequence at the i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 19). after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit which is a data direction bit (r/w) (figure 16). the most significant five bits of the slave address are fixed as ?00100?. the next two bits are cad1 and cad0 (chip address bits). the bits identify the specific device on the bus. the hard-wired input pins (cad1 and cad0 pins) set them. if the slave address match that of the AK4348 and r/w bit is ?0?, the AK4348 generates the acknowledge and the write operation is executed. if r/w bit is ?1?, the AK4348 generates the not acknowledge since the AK4348 can be only a slave-receiver. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 20). the second byte consists of the address for control registers of the AK4348. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 17). those data after the second byte contain control data. the format is msb first, 8bits (figure 18). the AK4348 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 19). the AK4348 is capable of more than one byte write operation by one sequence. after r eceipt of the third byte, the AK4348 generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. if the addresses exceed 1fh prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 21) except for the start and the stop condition. sda s t a r t a c k a c k s slave address a c k sub address(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w a c k figure 15. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 cad1 cad0 r/w (those cad1/0 should match with cad1/0 pins) figure 16. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 17. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 18. byte structure after the second byte
asahi kasei [AK4348] ms0532-e-00 2006/07 - 22 - scl sda stop condition start condition sp figure 19. start and stop conditions scl from master acknowled g e data output by master data output by slave(ak4359) 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 20. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 21. bit transfer on the i 2 c-bus
asahi kasei [AK4348] ms0532-e-00 2006/07 - 23 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks tdm1 tdm0 dif2 dif1 dif0 pw1 rstn 01h control 2 0 0 slow dfs1 dfs0 dem1 dem0 smute 02h control 3 pw4 pw3 pw2 0 0 dzfb pw1 0 03h lout1 att control att7 att6 att5 att4 att3 att2 att1 att0 04h rout1 att control att7 att6 att5 att4 att3 att2 att1 att0 05h lout2 att control att7 att6 att5 att4 att3 att2 att1 att0 06h rout2 att control att7 att6 att5 att4 att3 att2 att1 att0 07h lout3 att control att7 att6 att5 att4 att3 att2 att1 att0 08h rout3 att control att7 att6 att5 att4 att3 att2 att1 att0 09h lout4 att control att7 att6 att5 att4 att3 att2 att1 att0 0ah rout4 att control att7 att6 att5 att4 att3 att2 att1 att0 0bh invert output signal invl1 invr1 invl2 invr2 invl3 invr3 invl4 invr4 0ch dzf1 control l1 r1 l2 r2 l3 r3 l4 r4 0dh dzf2 control l1 r1 l2 r2 l3 r3 l4 r4 0eh dem control 0 0 0 0 dema demb demc demd note: for addresses from 0fh to 1fh, data must not be written. when rstb pin goes to ?l?, the registers are initialized to their default values. when rstn bit goes to ?0?, the only internal timing is reset, and the registers are not initialized to their default values. all data can be written to the registers even if pw1-4 bits or rstn bit is ?0?. ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks tdm1 tdm0 dif2 dif1 dif0 pw1 rstn default 1 0 0 0 1 0 1 1 rstn: internal timing reset 0: reset. all dzf pins go to ?h? and any registers are not initialized. 1: normal operation when mclk frequency or dfs changes, the click noise can be reduced by rstn bit. pw1: power-down control (0: power-down, 1: power-up) pw1: power down control of dac1 this bit is duplicated into d1 of 02h. dif2-0: audio data interface modes (see table 7, table 8) initial: ?010?, mode 2 tdm0-1: tdm mode select mode tdm1 tdm0 bick sdti sampling speed normal 0 0 32fs 1-4 normal, double, quad speed tdm256 0 1 256fs fixed 1 normal speed tdm128 1 1 128fs fixed 1-2 normal, double speed acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically when the acks bit = ?1?. in this case, the setting of dfs1-0 bits is ignored. when this bit is ?0?, dfs1-0 bits set the sampling speed mode.
asahi kasei [AK4348] ms0532-e-00 2006/07 - 24 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 slow dfs1 dfs0 dem1 dem0 smute default 0 0 0 0 0 0 1 0 smute: soft mute enable 0: normal operation 1: dac outputs soft-muted dem1-0: de-emphasis response (see table 9) initial: ?01?, off dfs1-0: sampling speed control (see table 1) 00: normal speed 01: double speed 10: quad speed when changing between normal/double speed mode and quad speed mode, some click noise occurs. slow: slow roll-off filter enable 0: sharp roll-off filter 1: slow roll-off filter adr register name d7 d6 d5 d4 d3 d2 d1 d0 02h speed & power down control pw4 pw3 pw2 0 0 dzfb pw1 0 default 1 1 1 0 0 0 1 0 pw1: power-down control (0: power-down, 1: power-up) pw1: power down control of dac1 this bit is duplicated into d1 of 00h. dzfb: inverting enable of dzf 0: dzf goes ?h? at zero detection 1: dzf goes ?l? at zero detection pw4-2: power-down control (0: power-down, 1: power-up) pw2: power down control of dac2 pw3: power down control of dac3 pw4: power down control of dac4 all sections are powered-down by pw1=pw2=pw3=pw4=0.
asahi kasei [AK4348] ms0532-e-00 2006/07 - 25 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lout1 att control att7 att6 att5 att4 att3 att2 att1 att0 04h rout1 att control att7 att6 att5 att4 att3 att2 att1 att0 05h lout2 att control att7 att6 att5 att4 att3 att2 att1 att0 06h rout2 att control att7 att6 att5 att4 att3 att2 att1 att0 07h lout3 att control att7 att6 att5 att4 att3 att2 att1 att0 08h rout3 att control att7 att6 att5 att4 att3 att2 att1 att0 09h lout4 att control att7 att6 att5 att4 att3 att2 att1 att0 0ah rout4 att control att7 att6 att5 att4 att3 att2 att1 att0 default 1 1 1 1 1 1 1 1 att = 20 log 10 (att_data / 255) [db] 00h: mute addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh invert output signal invl1 invr1 invl2 invr2 invl3 invr3 invl4 invr4 default 0 0 0 0 0 0 0 0 invl1-4, invr1-4: inverting output polarity 0: normal output 1: inverted output addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch dzf1 control l1 r1 l2 r2 l3 r3 l4 r4 0dh dzf2 control l1 r1 l2 r2 l3 r3 l4 r4 default 0 0 0 0 0 0 0 0 l1-4, r1-4: zero detect flag enable for dzf1/2 pins 0: disable 1: enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh dem control 0 0 0 0 dema demb demc demd default 0 0 0 0 0 0 0 0 dema-d: de-emphasis enable of dac1/2/3/4 0: disable 1: enable
asahi kasei [AK4348] ms0532-e-00 2006/07 - 26 - system design figure 22 and 23 shows the system connection diagram. an evaluation board (akd4348) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. bick 2 sdti1 3 lrck 4 rstb 5 smute 6 acks 7 dif0 8 sdti2 9 sdti3 10 sdti4 11 dif1 12 dem0 13 tdm0 29 avdd 28 avss 27 vcom 26 lout1 25 rout1 24 p/s 23 lout2 22 rout2 21 lout3 20 rout3 19 lout4 18 micro- controller 0.1u AK4348 mute signal 14 15 17 16 dvdd dvss rout4 dem1 r1ch out l1ch out analog ground digital ground l2ch out r2ch out master clock fs 24bit audio data 64fs reset 24bit audio data 24bit audio data + 10u + 0.1u 10u digital 3.3v mclk 1 dzf1 30 24bit audio data mute mute mute mute mute mute mute mute l3ch out r3ch out l4ch out r4ch out 0.1u + 10u micro- controller micro-controller analog 3.3v tdm mode figure 22. typical connection diagram (parallel control mode) notes: - lrck = fs, bick = 64fs. - when lout/rout drives some capacitive load, some resistor should be added in series between lout/rout and capacitive load. - all input pins except p/s and tdm0 pins should not be left floating.
asahi kasei [AK4348] ms0532-e-00 2006/07 - 27 - bick 2 sdti1 3 lrck 4 rstb 5 csn 6 cclk 7 cdti 8 sdti2 9 sdti3 10 sdti4 11 dif1 12 cad0 13 dzf2 29 avdd 28 avss 27 vcom 26 lout1 25 rout1 24 p/s 23 lout2 22 rout2 21 lout3 20 rout3 19 lout4 18 micro- controller 0.1u AK4348 analog 3.3v 14 15 17 16 dvdd dvss rout4 i2c r1ch out l1ch out analog ground digital ground l2ch out r2ch out master clock fs 24bit audio data 64fs reset 24bit audio data 24bit audio data + + 0.1u 10u digital 3.3v mclk 1 dzf1 30 24bit audio data mute mute mute mute mute mute mute mute l3ch out r3ch out l4ch out r4ch out 0.1u + 10u micro- controller 10u figure 23. typical connection diagram (3-wire serial control mode) notes: - lrck = fs, bick = 64fs. - when lout/rout drives some capacitive load, some resistor should be added in series between lout/rout and capacitive load. - all input pins except p/s pin should not be left floating. - dzf1 pin goes to ?h? when zero data input is detected or smute bit is set to ?1?.
asahi kasei [AK4348] ms0532-e-00 2006/07 - 28 - analog ground digital ground system controller bick sdti1 3 lrck 4 rstb 5 smute/csn/cad0 6 acks/cclk/csl 7 dfs0/cdt/sda 8 sdti2 9 sdti3 10 sdti4 11 dif1 12 dem0/cad1 13 tdm0/dzf2 29 avdd 28 avss 27 vcom 26 lout1 25 rout1 24 p/s 23 lout2 22 rout2 21 lout3 20 rout3 19 lout4 AK4348 18 14 15 17 16 dvdd dvss rout4 dem1/i2 mclk dzf1 30 2 1 figure 24. ground layout avss and dvss must be connected to the same analog ground plane. 1. grounding and power supply decoupling avdd and dvdd are usually supplied from the analog supply in the system and it should be separated from system digital supply. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss and dvss of the AK4348 must be connected to the analog ground plane . system analog ground and digital ground should be connected together close to where the supplies are brought onto the printed circuit board. a decoupling capacitor, typically a 0.1 f ceramic capacitor for high frequency bypass, should be placed as near to avdd and dvdd as possible. 2. analog outputs the analog outputs are single-ended and centered around the vcom voltage. the output signal range is typically 2.24vpp (when avdd=3.3v). the phase of the analog outputs can be inverted channel independently by the invl/invr bits. the internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. the input data format is 2?s complement. the output voltage is a positive full scale for 7fffffh (@24-bit) and a negative full scale for 800000h (@24-bit). the ideal output is vcom voltage for 000000h (@24-bit). dc offsets on the analog outputs are eliminated by ac coupling since the analog outputs have dc offsets of vcom + a few mv.
asahi kasei [AK4348] ms0532-e-00 2006/07 - 29 - package detail a note: dimension "*" does not include mold flash. 0.22 0.1 0.65 *9.7 0.1 1.5max a 1 15 16 30 30pin vsop (unit: mm) 5.6 0.1 7.6 0.2 0.45 0.2 -0.05 +0.10 0.3 0.15 0.12 m 0.08 1.2 0.10 0.10 +0.10 -0.05 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [AK4348] ms0532-e-00 2006/07 - 30 - marking (AK4348ef) akm a k4348ef xxxbyyyyc xxxbyyyyc date code identifier xxxb: lot number (x: digit number, b: alpha character) yyyyc: assembly date (y: digit number, c: alpha character)
asahi kasei [AK4348] ms0532-e-00 2006/07 - 31 - marking (AK4348vf) akm a k4348vf xxxbyyyyc xxxbyyyyc date code identifier xxxb: lot number (x: digit number, b: alpha character) yyyyc: assembly date (y: digit number, c: alpha character) date (yy/mm/dd) revision reason page contents 06/07/28 00 first edition important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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